In advanced technology nodes of integrated circuit industry, the critical dimensions of semiconductor devices become smaller and smaller. Various new compositions and structures are adopted. For examples, a high k dielectric material and metal are used to form a gate stack of a field-effect transistor (FET) such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Three dimensional (3D) fin field effect transistors (FINFETs) are also used. However, in the FINFETs, the fin active regions are extruded above the semiconductor substrate. It is challenging to control the height of the fin active regions uniformly from wafer to wafer, lot to lot, product to product. Accordingly, the circuit performance and quality are impacted. For example, in existing methods to form the metal gate stack, metal gates are formed in a gate-replacement process that removes dummy gates and fills in the gate trenches with gate materials. Due to high packing density and small feature sizes, it is challenging to achieve proper gap filling and profile control, especially for the FINFETs.
Therefore, a method and system to form integrated circuits of FINFETs are needed to address the issues identified above.